Decreased power consumption of dynamic random access memory (DRAM) devices during a standby, or self-refresh mode of operation is becoming increasingly important because of their ever-growing use in mobile applications. One technique to decrease power consumption is to reduce the refresh current supplied to individual memory cells of the device. Another approach is to minimize charge pump related leakage currents typically existing in row decoder circuits of conventional DRAM memory devices.
DRAM memory devices generally employ a row decoder circuit comprising a decoding unit and a wordline driver to drive a voltage level of a wordline high or low in order to “open” or “close” access to an associated row of memory cells. Typically, such circuits operate to drive the wordline voltage level between a range of a positive voltage (VPP), which is greater than a maximum available power supply voltage (VCC), and a negative voltage (VNEG), which is less than a reference voltage (VSS), such as a ground reference. By utilizing VNEG rather than VSS, the threshold level of data cell access transistors can be reduced, resulting in reduced stress on the access transistors and enabling a reduction in the VPP level.
Typically, based on row address signals and a precharge signal, the wordline driver drives an associated wordline at VPP (“high”) to open a row of memory cells to enable read/write access to the memory cells, and at VNEG (“low”) to close a row of memory cells. During periods of read/write inactivity, the wordline driver operates in an idle mode, sometimes referred to as a retention or self-refresh mode, and closes the row of memory cells by maintaining the wordline at VNEG when the associated row is not selected to be refreshed.
FIG. 1 is a schematic diagram depicting one example of a conventional row decoder circuit 30. Row decoder circuit 30 comprises a decoding unit 32 and a wordline driver circuit 34. Row decoder circuit 32 includes a PMOS transistor 36 and a cascade of NMOS transistors 38, 40, and 42. PMOS transistor 36 receives a bar precharge signal (bPRCH) at gate, has a drain coupled to a decoding node 44, and has a source. The drain of NMOS transistor 38 is coupled to decoding node 44 and the source is coupled to the drain of NMOS transistor 40. The drain NMOS transistor 42 is coupled to the source of NMOS transistor 40 and the source is coupled to ground. The gates of NMOS transistors 38, 40, and 42 respectively receive address inputs XA23, XA45, and XA678. Address inputs XA23, XA45, and XA678 represent address lines two through eight of a memory bus of an associated memory device, such as a DRAM memory device, in precoded form.
Wordline driver 34 includes PMOS transistors 46, 48, 50, and 52, NMOS transistors 54, 56, and 58, a positive voltage node 60, a negative voltage node 62, a bar decode node (bdec) 64, and an output node 66. Wordline driver 34 receives positive voltage VPP at positive voltage node 60 and negative voltage VNEG at negative voltage node 62, and provides a bar wordline signal (bMWL) to a corresponding row of an associated memory array at output node 66.
During standby, or self-refresh mode, which comprises a large portion of semiconductor memory device operating time, bPRCH is held “low”, causing PMOS transistor 36 to turn on and node dec 44 to be set at VPP. With node dec 44 at VPP, PMOS transistor 50 is turned off and PMOS transistor 48 is turned on, thereby setting the gate of NMOS transistor 56 at VPP. With its gate set at VPP, NMOS transistor 56 is turned on, thereby setting node ndec 64 to at VNEG. With node bdec 64 at VNEG, NMOS transistor 58 is turned off and PMOS transistor 52 is turned on, thereby setting output node 66, an thus bMWL, to VPP. With bMWL set at VPP, the corresponding memory array row is held closed.
With node bdec 64 set at VNEG, PMOS transistor 46 is also turned on. PMOS transistor 46 thereby functions as a latch to hold node dec 44 at VPP during self-refresh mode when bPRCH is set “high” but the corresponding memory array row is not selected for refresh.
While row decoder circuit 30 functions to hold the corresponding memory array row closed during self-refresh mode, except when the corresponding row is selected for refresh, wordline driver 34 forms a current leakage path from positive voltage node 60 to negative voltage node 62 via PMOS transistor 50 and NMOS transistor 56. Typically, VPP is provided by a positive charge pump and VNEG is provided by a negative charge pump, which are coupled to the wordline driver. Thus, during self-refresh mode, a leakage current flows from the positive charge pump coupled at positive voltage node 60 to the negative charge pump coupled at negative voltage node 62.
FIG. 2 is a block diagram 80 illustrating generally a leakage current path 82 from a positive charge pump 84 to a negative charge pump 86 formed by wordline driver 30 during idle mode. Lines 87 and 88 respectively represent a VPP supply rail and a VNEG supply rail within a corresponding semiconductor memory device, such as a DRAM memory device. Leakage path 82 is coupled between VPP supply rail 87 and VNEG supply rail 88 via positive voltage node 60 and negative voltage node 62. A leakage current (ILEAK) 89 flows from positive voltage node 60 into negative voltage node 62.
ILEAK 89 flowing out of node 60 and into node 62 causes VPP to drop and VNEG to rise, thereby causing both positive charge pump 84 and negative charge pump 86 to consume power to maintain VPP and VNEG at desired levels. Typically, charge pumps have low efficiencies, often in the range of 40-50%, and thus consume more than just the power lost via ILEAK in maintaining their output voltages at desired levels. For example, a charge pump having an efficiency of 50% will consume 2*ILEAK of power in maintaining its output voltage at the desired level.
Semiconductor memory devices, particularly DRAM memory devices, would benefit from a more efficient wordline driver.